In such known switching elements buffer means can generally be associated with the signal inputs and/or with the signal outputs. In case they are associated with the signal inputs, when several signals arrive at a same signal input and have to be transmitted to a same signal output, the corresponding input buffer means may only be emptied at the signal transmission speed used on this signal output. This means that the following signals also arriving at this signal input and to be transmitted to another signal output have to wait for the completion of the transmission of the above preceding signals prior to being transmitted to their destination signal output even if the latter is not used.
In the switching element known from the PCT application published under No WO87/004579 and used in an Asynchronous Time Division (ATD) packet or cell switching system, buffer means associated with the signal outputs are preferred to avoid such input saturation. However, it requires at each of its signal outputs relatively large buffer means able to store signals simultaneously transmitted by all its signal inputs. Moreover, in order to be able to accept the signals from all the signal inputs, this known switching element operates at a speed or bitrate equal to the sum of the bitrates at which these signals are supplied at their respective signal input. As a result, the complexity of the element is increased.
A solution to reduce this switching speed and accordingly to decrease the complexity of the switching element is for instance proposed in the PCT/EP88/00212 application filed on Mar. 11, 1988 and consists in subdividing each of the input signals into a number of parts, particularly sub packets in an AID system. Thus, the switching speed of the element is also divided by the same number. However, additional circuits required to realise such subdivision and to combine these parts into an output signal also contribute to the complexity of the switching element.
In the article: "Packet Switching Interconnection Networks for Modular Systems" by D. M. Dias et al published in IEEE-COMPUTER of December 1981, pages 43 to 53, and more particularly on page 45 thereof, delta networks are considered wherein the links between stages of a packet switching network contain data buffers organized as first-in-first-out queues and each able to hold one or more packets. In this way the two signal inputs and the two signal outputs of a binary switching element part of an intermediate stage are each associated with such a buffer. Nevertheless, blocking can still occur for such a switching element when the buffer at one of its output terminals is full.
In the article "THE KNOCKOUT SWITCH: A SIMPLE, MODULAR ARCHITECTURE FOR HIGH-PERFORMANCE PACKET SWITCHING" by Y. S. Yeh et al published in the proceedings of ISS '87 pages 0801 to 0808 as well as in the European patent application by the same inventors published under No. 0256702, a so-called N-input, N-output "knockout" packet switch uses N output interface units, each with N packet filters associated with the N signal inputs, a concentrator which achieves an N to L concentration, with L&lt;&lt;N, and an output buffer in order to have a lost packet rate as small as desired. However, if more than L packets or cells for the same signal output arrive simultaneously on the signal inputs, the extra packets are lost, even at a low transmission rate. Moreover, the modularity advantage of this known system increasing with the size thereof, it will preferably be used in large switching systems.
The present invention more particularly relates to a communication switching element for transferring digital signals, grouped in cells, from a plurality of signal inputs to a plurality of signal outputs, said switching element including a plurality of buffer means each associated and permanently dedicated to a distinct connection between any predetermined pair of signal input and signal output, and including a plurality of priority circuits each interconnecting the buffer means of a respective associated set and each allowing said transfers one at a time from the buffer means of said associated set.
Such a switching element is already known in the art, e.g. from the International Patent Application WO86/02510 published on Apr. 24, 1986. Therein, all the signal inputs are simultaneously able to transfer their input signals to the dedicated buffer means used. Hence, the speed of transmission of the signals between an input and an output never needs to exceed the speed of the input signals and thus no additional speed reduction circuit is required. Moreover, because each signal output uses a plurality of buffer means which are each dedicated to a distinct signal input and only receive signals therefrom, the size of these buffer means may be relatively small. Furthermore, the priority circuits thereof allow the cells or packets to exit from the buffer means either in the order of their arrival therein or according to a priority scheme by which the cell having the highest priority exits first.
This means that in the known switching element the buffer means are emptied either in sequence when all the cells have a same priority or in an order dependent on the degree of priority of each particular cell.
A problem with the known switching element is that, when for instance there is a high cell traffic between a particular signal input and a particular signal output, the corresponding buffer means could be filled faster than they are emptied. Indeed, in case all the cells have a same priority and the buffer means of a same set are thus emptied in sequence, the above fastly filled buffer means could rapidly overflow whereby some cells may be lost. Moreover, when the cells have different degrees of priority and when for instance most of the cells having a low priority degree are loaded in the above high traffic buffer means, the risk of cell loss is even greater.